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• HYD P tb / MCS loops    • pre-launch sw list
• BATT CHG → (CHG + PRE) (Mn Bus-off)
• aft mvn B cb
• timers

(1) gnd loop 
01B gnd ns s/c gnd
1. initial surge -> MCS loop cl
(add note to 2-2)
2. constant small V -> PROP P tb

• "surge" every time sw is moved to chg or chg tb
• may or may not be same @ [[at]] PAD
12.5 in PLB [[minus]]
5.1 PLB rtn
[[equals]] 7.4 "lost"

• tb does read correctly w/ [[with]] only SW PWR cb -in
• checking PROP P tb if curious (BATT-off): 
1. OK, but tell POCE
2. No prob cycling sw lots of time

• [[checkmark]] add to OPS support T/L  MCC calls about PROP P status

(2) CHG & PRE CKT has enough I to hold on S/C aft PLB 

[[image: diagram of a circuit? w/ labels]] 
aft PLB
CHG + PRE
CHG
01B is out of this CKT
MnBUS ON
MnBUS

* Move BATT-CHG (2-3) to 2-2 right after Mn bus - on  add NOTE: MCS loops close when batt chg moved from off

notes in C/L: 
1. RMS [[?]] - (INT)
2. PROP P tb - DN